/* * Intel WiFi Link driver. * * Written without any documentation but Damien Bergaminis * OpenBSD iwn(4) driver sources. Requires intel firmware * to be present in /lib/firmware/iwn-* on attach. * * not 64-bit clean */ #include "u.h" #include "../port/lib.h" #include "mem.h" #include "dat.h" #include "fns.h" #include "io.h" #include "../port/error.h" #include "../port/netif.h" #include "etherif.h" #include "wifi.h" enum { Ntxlog = 8, Ntx = 1<nic+((r)/4))) #define csr32w(c, r, v) (*((c)->nic+((r)/4)) = (v)) static uint get16(uchar *p) { return *((u16int*)p); } static uint get32(uchar *p) { return *((u32int*)p); } static void put32(uchar *p, uint v) { *((u32int*)p) = v; } static void put16(uchar *p, uint v) { *((u16int*)p) = v; }; static char* niclock(Ctlr *ctlr) { int i; csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | MacAccessReq); for(i=0; i<1000; i++){ if((csr32r(ctlr, Gpc) & (NicSleep | MacAccessEna)) == MacAccessEna) return 0; delay(10); } return "niclock: timeout"; } static void nicunlock(Ctlr *ctlr) { csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) & ~MacAccessReq); } static u32int prphread(Ctlr *ctlr, uint off) { csr32w(ctlr, PrphRaddr, ((sizeof(u32int)-1)<<24) | off); coherence(); return csr32r(ctlr, PrphRdata); } static void prphwrite(Ctlr *ctlr, uint off, u32int data) { csr32w(ctlr, PrphWaddr, ((sizeof(u32int)-1)<<24) | off); coherence(); csr32w(ctlr, PrphWdata, data); } static u32int memread(Ctlr *ctlr, uint off) { csr32w(ctlr, MemRaddr, off); coherence(); return csr32r(ctlr, MemRdata); } static void memwrite(Ctlr *ctlr, uint off, u32int data) { csr32w(ctlr, MemWaddr, off); coherence(); csr32w(ctlr, MemWdata, data); } static void setfwinfo(Ctlr *ctlr, uchar *d, int len) { FWInfo *i; if(len < 32) return; i = &ctlr->fwinfo; i->minjor = *d++; i->major = *d++; d += 2+8; i->type = *d++; i->subtype = *d++; d += 2; i->logptr = get32(d); d += 4; i->errptr = get32(d); d += 4; i->tstamp = get32(d); d += 4; i->valid = get32(d); }; static void dumpctlr(Ctlr *ctlr) { u32int dump[13]; int i; if(ctlr->fwinfo.errptr == 0){ print("no error pointer\n"); return; } for(i=0; ifwinfo.errptr + i*4); print( "error:\tid %ux, pc %ux,\n" "\tbranchlink %.8ux %.8ux, interruptlink %.8ux %.8ux,\n" "\terrordata %.8ux %.8ux, srcline %ud, tsf %ux, time %ux\n", dump[1], dump[2], dump[4], dump[3], dump[6], dump[5], dump[7], dump[8], dump[9], dump[10], dump[11]); } static char* eepromlock(Ctlr *ctlr) { int i, j; for(i=0; i<100; i++){ csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | EepromLocked); for(j=0; j<100; j++){ if(csr32r(ctlr, Cfg) & EepromLocked) return 0; delay(10); } } return "eepromlock: timeout"; } static void eepromunlock(Ctlr *ctlr) { csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) & ~EepromLocked); } static char* eepromread(Ctlr *ctlr, void *data, int count, uint off) { uchar *out = data; u32int w; int i; w = 0; for(; count > 0; count -= 2, off++){ csr32w(ctlr, EepromIo, off << 2); for(i=0; i<10; i++){ w = csr32r(ctlr, EepromIo); if(w & 1) break; delay(5); } if(i == 10) return "eepromread: timeout"; *out++ = w >> 16; if(count > 1) *out++ = w >> 24; } return 0; } static char* handover(Ctlr *ctlr) { int i; csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady); for(i=0; i<5; i++){ if(csr32r(ctlr, Cfg) & NicReady) return 0; delay(10); } csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | Prepare); for(i=0; i<15000; i++){ if((csr32r(ctlr, Cfg) & PrepareDone) == 0) break; delay(10); } if(i >= 15000) return "handover: timeout"; csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | NicReady); for(i=0; i<5; i++){ if(csr32r(ctlr, Cfg) & NicReady) return 0; delay(10); } return "handover: timeout"; } static char* clockwait(Ctlr *ctlr) { int i; /* Set "initialization complete" bit. */ csr32w(ctlr, Gpc, csr32r(ctlr, Gpc) | InitDone); for(i=0; i<2500; i++){ if(csr32r(ctlr, Gpc) & MacClockReady) return 0; delay(10); } return "clockwait: timeout"; } static char* poweron(Ctlr *ctlr) { int capoff; char *err; /* Disable L0s exit timer (NMI bug workaround). */ csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | DisL0Stimer); /* Don't wait for ICH L0s (ICH bug workaround). */ csr32w(ctlr, Giochicken, csr32r(ctlr, Giochicken) | L1AnoL0Srx); /* Set FH wait threshold to max (HW bug under stress workaround). */ csr32w(ctlr, Dbghpetmem, csr32r(ctlr, Dbghpetmem) | 0xffff0000); /* Enable HAP INTA to move adapter from L1a to L0s. */ csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | HapwakeL1A); capoff = pcicap(ctlr->pdev, PciCapPCIe); if(capoff != -1){ /* Workaround for HW instability in PCIe L0->L0s->L1 transition. */ if(pcicfgr16(ctlr->pdev, capoff + 0x10) & 0x2) /* LCSR -> L1 Entry enabled. */ csr32w(ctlr, Gio, csr32r(ctlr, Gio) | EnaL0S); else csr32w(ctlr, Gio, csr32r(ctlr, Gio) & ~EnaL0S); } if(ctlr->type != Type4965 && ctlr->type <= Type1000) csr32w(ctlr, AnaPll, csr32r(ctlr, AnaPll) | 0x00880300); /* Wait for clock stabilization before accessing prph. */ if((err = clockwait(ctlr)) != nil) return err; if((err = niclock(ctlr)) != nil) return err; /* Enable DMA and BSM (Bootstrap State Machine). */ if(ctlr->type == Type4965) prphwrite(ctlr, ApmgClkEna, DmaClkRqt | BsmClkRqt); else prphwrite(ctlr, ApmgClkEna, DmaClkRqt); delay(20); /* Disable L1-Active. */ prphwrite(ctlr, ApmgPciStt, prphread(ctlr, ApmgPciStt) | (1<<11)); nicunlock(ctlr); return 0; } static int iwlinit(Ether *edev) { Ctlr *ctlr; char *err; uchar b[2]; uint u; ctlr = edev->ctlr; if((err = handover(ctlr)) != nil) goto Err; if((err = poweron(ctlr)) != nil) goto Err; if((csr32r(ctlr, EepromGp) & 0x7) == 0){ err = "bad rom signature"; goto Err; } if((err = eepromlock(ctlr)) != nil) goto Err; if((err = eepromread(ctlr, edev->ea, sizeof(edev->ea), 0x15)) != nil){ eepromunlock(ctlr); goto Err; } if(ctlr->type != Type4965){ if((err = eepromread(ctlr, b, 2, 0x048)) != nil){ eepromunlock(ctlr); goto Err; } u = get16(b); ctlr->rfcfg.type = u & 3; u >>= 2; ctlr->rfcfg.step = u & 3; u >>= 2; ctlr->rfcfg.dash = u & 3; u >>= 4; ctlr->rfcfg.txantmask = u & 15; u >>= 4; ctlr->rfcfg.rxantmask = u & 15; if((err = eepromread(ctlr, b, 4, 0x128)) != nil){ eepromunlock(ctlr); goto Err; } ctlr->eeprom.crystal = get32(b); } eepromunlock(ctlr); switch(ctlr->type){ case Type4965: ctlr->rfcfg.txantmask = 3; ctlr->rfcfg.rxantmask = 7; break; case Type5100: ctlr->rfcfg.txantmask = 2; ctlr->rfcfg.rxantmask = 3; break; case Type6000: if(ctlr->pdev->did == 0x422c || ctlr->pdev->did == 0x4230){ ctlr->rfcfg.txantmask = 6; ctlr->rfcfg.rxantmask = 6; } break; } ctlr->ie = 0; csr32w(ctlr, Isr, ~0); /* clear pending interrupts */ csr32w(ctlr, Imr, 0); /* no interrupts for now */ return 0; Err: print("iwlinit: %s\n", err); return -1; } static char* crackfw(FWImage *i, uchar *data, uint size, int alt) { uchar *p, *e; FWSect *s; memset(i, 0, sizeof(*i)); if(size < 4){ Tooshort: return "firmware image too short"; } p = data; e = p + size; i->rev = get32(p); p += 4; if(i->rev == 0){ uvlong altmask; if(size < (4+64+4+4+8)) goto Tooshort; if(memcmp(p, "IWL\n", 4) != 0) return "bad firmware signature"; p += 4; strncpy(i->descr, (char*)p, 64); i->descr[64] = 0; p += 64; i->rev = get32(p); p += 4; i->build = get32(p); p += 4; altmask = get32(p); p += 4; altmask |= (uvlong)get32(p) << 32; p += 4; while(alt > 0 && (altmask & (1ULL< e) goto Tooshort; switch(get16(p)){ case 1: s = &i->main.text; break; case 2: s = &i->main.data; break; case 3: s = &i->init.text; break; case 4: s = &i->init.data; break; case 5: s = &i->boot.text; break; default:s = &dummy; } p += 2; if(get16(p) != 0 && get16(p) != alt) s = &dummy; p += 2; s->size = get32(p); p += 4; s->data = p; if((p + s->size) > e) goto Tooshort; p += (s->size + 3) & ~3; } } else { if(((i->rev>>8) & 0xFF) < 2) return "need firmware api >= 2"; if(((i->rev>>8) & 0xFF) >= 3){ i->build = get32(p); p += 4; } if((p + 5*4) > e) goto Tooshort; i->main.text.size = get32(p); p += 4; i->main.data.size = get32(p); p += 4; i->init.text.size = get32(p); p += 4; i->init.data.size = get32(p); p += 4; i->boot.text.size = get32(p); p += 4; i->main.text.data = p; p += i->main.text.size; i->main.data.data = p; p += i->main.data.size; i->init.text.data = p; p += i->init.text.size; i->init.data.data = p; p += i->init.data.size; i->boot.text.data = p; p += i->boot.text.size; if(p > e) goto Tooshort; } return 0; } static FWImage* readfirmware(char *name) { uchar dirbuf[sizeof(Dir)+100], *data; char buf[128], *err; FWImage *fw; int n, r; Chan *c; Dir d; if(!iseve()) error(Eperm); if(!waserror()){ snprint(buf, sizeof buf, "/boot/%s", name); c = namec(buf, Aopen, OREAD, 0); poperror(); } else { snprint(buf, sizeof buf, "/lib/firmware/%s", name); c = namec(buf, Aopen, OREAD, 0); } if(waserror()){ cclose(c); nexterror(); } n = c->dev->stat(c, dirbuf, sizeof dirbuf); if(n <= 0) error("can't stat firmware"); convM2D(dirbuf, n, &d, nil); fw = smalloc(sizeof(*fw) + 16 + d.length); data = (uchar*)(fw+1); if(waserror()){ free(fw); nexterror(); } r = 0; while(r < d.length){ n = c->dev->read(c, data+r, d.length-r, (vlong)r); if(n <= 0) break; r += n; } if((err = crackfw(fw, data, r, 1)) != nil) error(err); poperror(); poperror(); cclose(c); return fw; } typedef struct Irqwait Irqwait; struct Irqwait { Ctlr *ctlr; u32int mask; }; static int gotirq(void *arg) { Irqwait *w; Ctlr *ctlr; w = arg; ctlr = w->ctlr; ctlr->wait.r = ctlr->wait.m & w->mask; if(ctlr->wait.r){ ctlr->wait.m &= ~ctlr->wait.r; return 1; } ctlr->wait.w = w->mask; return 0; } static u32int irqwait(Ctlr *ctlr, u32int mask, int timeout) { Irqwait w; w.ctlr = ctlr; w.mask = mask; tsleep(&ctlr->wait, gotirq, &w, timeout); ctlr->wait.w = 0; return ctlr->wait.r & mask; } static char* loadfirmware1(Ctlr *ctlr, u32int dst, uchar *data, int size) { uchar *dma; char *err; dma = mallocalign(size, 16, 0, 0); if(dma == nil) return "no memory for dma"; memmove(dma, data, size); coherence(); if((err = niclock(ctlr)) != 0){ free(dma); return err; } csr32w(ctlr, FhTxConfig + 9*32, 0); csr32w(ctlr, FhSramAddr + 9*4, dst); csr32w(ctlr, FhTfbdCtrl0 + 9*8, PCIWADDR(dma)); csr32w(ctlr, FhTfbdCtrl1 + 9*8, size); csr32w(ctlr, FhTxBufStatus + 9*32, (1<fw; if(fw->boot.text.size == 0){ if((err = loadfirmware1(ctlr, 0x00000000, fw->main.text.data, fw->main.text.size)) != nil) return err; if((err = loadfirmware1(ctlr, 0x00800000, fw->main.data.data, fw->main.data.size)) != nil) return err; csr32w(ctlr, Reset, 0); goto bootmain; } size = ROUNDUP(fw->init.data.size, 16) + ROUNDUP(fw->init.text.size, 16); dma = mallocalign(size, 16, 0, 0); if(dma == nil) return "no memory for dma"; if((err = niclock(ctlr)) != nil){ free(dma); return err; } p = dma; memmove(p, fw->init.data.data, fw->init.data.size); coherence(); prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4); prphwrite(ctlr, BsmDramDataSize, fw->init.data.size); p += ROUNDUP(fw->init.data.size, 16); memmove(p, fw->init.text.data, fw->init.text.size); coherence(); prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4); prphwrite(ctlr, BsmDramTextSize, fw->init.text.size); nicunlock(ctlr); if((err = niclock(ctlr)) != nil){ free(dma); return err; } p = fw->boot.text.data; n = fw->boot.text.size/4; for(i=0; imain.data.size, 16) + ROUNDUP(fw->main.text.size, 16); dma = mallocalign(size, 16, 0, 0); if(dma == nil) return "no memory for dma"; if((err = niclock(ctlr)) != nil){ free(dma); return err; } p = dma; memmove(p, fw->main.data.data, fw->main.data.size); coherence(); prphwrite(ctlr, BsmDramDataAddr, PCIWADDR(p) >> 4); prphwrite(ctlr, BsmDramDataSize, fw->main.data.size); p += ROUNDUP(fw->main.data.size, 16); memmove(p, fw->main.text.data, fw->main.text.size); coherence(); prphwrite(ctlr, BsmDramTextAddr, PCIWADDR(p) >> 4); prphwrite(ctlr, BsmDramTextSize, fw->main.text.size | (1<<31)); nicunlock(ctlr); bootmain: if(irqwait(ctlr, Ierr|Ialive, 5000) != Ialive){ free(dma); return "main firmware boot failed"; } free(dma); return nil; } static int txqready(void *arg) { TXQ *q = arg; return q->n < Ntx; } static void qcmd(Ctlr *ctlr, uint qid, uint code, uchar *data, int size, Block *block) { uchar *d, *c; TXQ *q; assert(qid < nelem(ctlr->tx)); assert(size <= Tcmdsize-4); ilock(ctlr); q = &ctlr->tx[qid]; while(q->n >= Ntx){ iunlock(ctlr); qlock(q); if(!waserror()){ tsleep(q, txqready, q, 10); poperror(); } qunlock(q); ilock(ctlr); } q->n++; q->b[q->i] = block; c = q->c + q->i * Tcmdsize; d = q->d + q->i * Tdscsize; /* build command */ c[0] = code; c[1] = 0; /* flags */ c[2] = q->i; c[3] = qid; memmove(c+4, data, size); size += 4; /* build descriptor */ *d++ = 0; *d++ = 0; *d++ = 0; *d++ = 1 + (block != nil); /* nsegs */ put32(d, PCIWADDR(c)); d += 4; put16(d, size << 4); d += 2; if(block != nil){ size = BLEN(block); if(size > Tbufsize) size = Tbufsize; put32(d, PCIWADDR(block->rp)); d += 4; put16(d, size << 4); } coherence(); q->i = (q->i+1) % Ntx; csr32w(ctlr, HbusTargWptr, (qid<<8) | q->i); iunlock(ctlr); } static int txqempty(void *arg) { TXQ *q = arg; return q->n == 0; } static void flushq(Ctlr *ctlr, uint qid) { TXQ *q; q = &ctlr->tx[qid]; while(q->n > 0){ qlock(q); if(!waserror()){ tsleep(q, txqempty, q, 10); poperror(); } qunlock(q); } } static void flushcmd(Ctlr *ctlr) { flushq(ctlr, 4); } static void cmd(Ctlr *ctlr, uint code, uchar *data, int size) { qcmd(ctlr, 4, code, data, size, nil); } static void setled(Ctlr *ctlr, int which, int on, int off) { uchar c[8]; csr32w(ctlr, Led, csr32r(ctlr, Led) & ~LedBsmCtrl); memset(c, 0, sizeof(c)); put32(c, 10000); c[4] = which; c[5] = on; c[6] = off; cmd(ctlr, 72, c, sizeof(c)); } /* * initialization which runs after the firmware has been booted up */ static void postboot(Ctlr *ctlr) { uint ctxoff, ctxlen, dramaddr, txfact; uchar c[8]; char *err; int i, q; if((err = niclock(ctlr)) != nil) error(err); if(ctlr->type != Type4965){ dramaddr = SchedDramAddr5000; ctxoff = SchedCtxOff5000; ctxlen = SchedCtxLen5000; txfact = SchedTxFact5000; } else { dramaddr = SchedDramAddr4965; ctxoff = SchedCtxOff4965; ctxlen = SchedCtxLen4965; txfact = SchedTxFact4965; } ctlr->sched.base = prphread(ctlr, SchedSramAddr); for(i=0; i < ctxlen; i += 4) memwrite(ctlr, ctlr->sched.base + ctxoff + i, 0); prphwrite(ctlr, dramaddr, PCIWADDR(ctlr->sched.s)>>10); csr32w(ctlr, FhTxChicken, csr32r(ctlr, FhTxChicken) | 2); if(ctlr->type != Type4965){ /* Enable chain mode for all queues, except command queue 4. */ prphwrite(ctlr, SchedQChainSel5000, 0xfffef); prphwrite(ctlr, SchedAggrSel5000, 0); for(q=0; q<20; q++){ prphwrite(ctlr, SchedQueueRdptr5000 + q*4, 0); csr32w(ctlr, HbusTargWptr, q << 8); memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 0); /* Set scheduler window size and frame limit. */ memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16 | 64); } /* Enable interrupts for all our 20 queues. */ prphwrite(ctlr, SchedIntrMask5000, 0xfffff); } else { /* Disable chain mode for all our 16 queues. */ prphwrite(ctlr, SchedQChainSel4965, 0); for(q=0; q<16; q++) { prphwrite(ctlr, SchedQueueRdptr4965 + q*4, 0); csr32w(ctlr, HbusTargWptr, q << 8); /* Set scheduler window size. */ memwrite(ctlr, ctlr->sched.base + ctxoff + q*8, 64); /* Set scheduler window size and frame limit. */ memwrite(ctlr, ctlr->sched.base + ctxoff + q*8 + 4, 64<<16); } /* Enable interrupts for all our 16 queues. */ prphwrite(ctlr, SchedIntrMask4965, 0xffff); } /* Identify TX FIFO rings (0-7). */ prphwrite(ctlr, txfact, 0xff); /* Mark TX rings (4 EDCA + cmd + 2 HCCA) as active. */ for(q=0; q<7; q++){ if(ctlr->type != Type4965){ static uchar qid2fifo[] = { 3, 2, 1, 0, 7, 5, 6 }; prphwrite(ctlr, SchedQueueStatus5000 + q*4, 0x00ff0018 | qid2fifo[q]); } else { static uchar qid2fifo[] = { 3, 2, 1, 0, 4, 5, 6 }; prphwrite(ctlr, SchedQueueStatus4965 + q*4, 0x0007fc01 | qid2fifo[q]<<1); } } nicunlock(ctlr); if(ctlr->type != Type4965){ if(ctlr->type != Type5150){ memset(c, 0, sizeof(c)); c[0] = 15; /* code */ c[1] = 0; /* grup */ c[2] = 1; /* ngroup */ c[3] = 1; /* isvalid */ put16(c+4, ctlr->eeprom.crystal); cmd(ctlr, 176, c, 8); } put32(c, ctlr->rfcfg.txantmask & 7); cmd(ctlr, 152, c, 4); } } static void addnode(Ctlr *ctlr, uchar id, uchar *addr) { uchar c[Tcmdsize], *p; memset(p = c, 0, sizeof(c)); *p++ = 0; /* control (1 = update) */ p += 3; /* reserved */ memmove(p, addr, 6); p += 6; p += 2; /* reserved */ *p++ = id; /* node id */ p++; /* flags */ p += 2; /* reserved */ p += 2; /* kflags */ p++; /* tcs2 */ p++; /* reserved */ p += 5*2; /* ttak */ p++; /* kid */ p++; /* reserved */ p += 16; /* key */ if(ctlr->type != Type4965){ p += 8; /* tcs */ p += 8; /* rxmic */ p += 8; /* txmic */ } p += 4; /* htflags */ p += 4; /* mask */ p += 2; /* disable tid */ p += 2; /* reserved */ p++; /* add ba tid */ p++; /* del ba tid */ p += 2; /* add ba ssn */ p += 4; /* reserved */ cmd(ctlr, 24, c, p - c); } void rxon(Ether *edev, Wnode *bss) { uchar c[Tcmdsize], *p; int filter, flags; Ctlr *ctlr; ctlr = edev->ctlr; filter = FilterMulticast | FilterBeacon; if(ctlr->prom){ filter |= FilterPromisc; bss = nil; } if(bss != nil){ ctlr->channel = bss->channel; memmove(ctlr->bssid, bss->bssid, Eaddrlen); ctlr->aid = bss->aid; if(ctlr->aid != 0){ filter |= FilterBSS; filter &= ~FilterBeacon; ctlr->bssnodeid = -1; } else ctlr->bcastnodeid = -1; } else { memmove(ctlr->bssid, edev->bcast, Eaddrlen); ctlr->aid = 0; ctlr->bcastnodeid = -1; ctlr->bssnodeid = -1; } flags = RFlagTSF | RFlagCTSToSelf | RFlag24Ghz | RFlagAuto; if(0) print("rxon: bssid %E, aid %x, channel %d, filter %x, flags %x\n", ctlr->bssid, ctlr->aid, ctlr->channel, filter, flags); memset(p = c, 0, sizeof(c)); memmove(p, edev->ea, 6); p += 8; /* myaddr */ memmove(p, ctlr->bssid, 6); p += 8; /* bssid */ memmove(p, edev->ea, 6); p += 8; /* wlap */ *p++ = 3; /* mode (STA) */ *p++ = 0; /* air (?) */ /* rxchain */ put16(p, ((ctlr->rfcfg.rxantmask & 7)<<1) | (2<<10) | (2<<12)); p += 2; *p++ = 0xff; /* ofdm mask (not yet negotiated) */ *p++ = 0x0f; /* cck mask (not yet negotiated) */ put16(p, ctlr->aid & 0x3fff); p += 2; /* aid */ put32(p, flags); p += 4; put32(p, filter); p += 4; *p++ = ctlr->channel; p++; /* reserved */ *p++ = 0xff; /* ht single mask */ *p++ = 0xff; /* ht dual mask */ if(ctlr->type != Type4965){ *p++ = 0xff; /* ht triple mask */ p++; /* reserved */ put16(p, 0); p += 2; /* acquisition */ p += 2; /* reserved */ } cmd(ctlr, 16, c, p - c); if(ctlr->bcastnodeid == -1){ ctlr->bcastnodeid = (ctlr->type != Type4965) ? 15 : 31; addnode(ctlr, ctlr->bcastnodeid, edev->bcast); } if(ctlr->bssnodeid == -1 && bss != nil && ctlr->aid != 0){ ctlr->bssnodeid = 0; addnode(ctlr, ctlr->bssnodeid, bss->bssid); } flushcmd(ctlr); } static struct ratetab { uchar rate; uchar plcp; uchar flags; } ratetab[] = { { 2, 10, RFlagCCK }, { 4, 20, RFlagCCK }, { 11, 55, RFlagCCK }, { 22, 110, RFlagCCK }, { 12, 0xd, 0 }, { 18, 0xf, 0 }, { 24, 0x5, 0 }, { 36, 0x7, 0 }, { 48, 0x9, 0 }, { 72, 0xb, 0 }, { 96, 0x1, 0 }, { 108, 0x3, 0 }, { 120, 0x3, 0 } }; enum { TFlagNeedProtection = 1<<0, TFlagNeedRTS = 1<<1, TFlagNeedCTS = 1<<2, TFlagNeedACK = 1<<3, TFlagLinkq = 1<<4, TFlagImmBa = 1<<6, TFlagFullTxOp = 1<<7, TFlagBtDis = 1<<12, TFlagAutoSeq = 1<<13, TFlagMoreFrag = 1<<14, TFlagInsertTs = 1<<16, TFlagNeedPadding = 1<<20, }; static void transmit(Wifi *wifi, Wnode *wn, Block *b) { uchar c[Tcmdsize], *p; Ether *edev; Ctlr *ctlr; Wifipkt *w; int flags, nodeid, rate; w = (Wifipkt*)b->rp; edev = wifi->ether; ctlr = edev->ctlr; qlock(ctlr); if(ctlr->prom == 0) if(wn->aid != ctlr->aid || wn->channel != ctlr->channel || memcmp(wn->bssid, ctlr->bssid, Eaddrlen) != 0) rxon(edev, wn); rate = 0; flags = 0; nodeid = ctlr->bcastnodeid; if((w->a1[0] & 1) == 0){ flags |= TFlagNeedACK; if(BLEN(b) > 512-4) flags |= TFlagNeedRTS; if((w->fc[0] & 0x0c) == 0x08 && ctlr->bssnodeid != -1){ nodeid = ctlr->bssnodeid; rate = 2; /* BUG: hardcode 11Mbit */ } if(flags & (TFlagNeedRTS|TFlagNeedCTS)){ if(ctlr->type != Type4965){ flags &= ~(TFlagNeedRTS|TFlagNeedCTS); flags |= TFlagNeedProtection; } else flags |= TFlagFullTxOp; } } qunlock(ctlr); memset(p = c, 0, sizeof(c)); put16(p, BLEN(b)); p += 2; p += 2; /* lnext */ put32(p, flags); p += 4; put32(p, 0); p += 4; /* scratch */ *p++ = ratetab[rate].plcp; *p++ = ratetab[rate].flags | (1<<6); p += 2; /* xflags */ *p++ = nodeid; *p++ = 0; /* security */ *p++ = 0; /* linkq */ p++; /* reserved */ p += 16; /* key */ p += 2; /* fnext */ p += 2; /* reserved */ put32(p, ~0); /* lifetime */ p += 4; /* BUG: scratch ptr? not clear what this is for */ put32(p, PCIWADDR(ctlr->kwpage)); p += 5; *p++ = 60; /* rts ntries */ *p++ = 15; /* data ntries */ *p++ = 0; /* tid */ put16(p, 0); /* timeout */ p += 2; p += 2; /* txop */ qcmd(ctlr, 0, 28, c, p - c, b); } static int rbplant(Ctlr *ctlr, int i) { Block *b; b = iallocb(Rbufsize + 256); if(b == nil) return -1; b->rp = b->wp = (uchar*)ROUNDUP((uintptr)b->base, 256); memset(b->rp, 0, Rdscsize); ctlr->rx.b[i] = b; ctlr->rx.p[i] = PCIWADDR(b->rp) >> 8; return 0; } static long iwlctl(Ether *edev, void *buf, long n) { Ctlr *ctlr; ctlr = edev->ctlr; if(ctlr->wifi) return wifictl(ctlr->wifi, buf, n); return 0; } static long iwlifstat(Ether *edev, void *buf, long n, ulong off) { Ctlr *ctlr; ctlr = edev->ctlr; if(ctlr->wifi) return wifistat(ctlr->wifi, buf, n, off); return 0; } static void setoptions(Ether *edev) { Ctlr *ctlr; char buf[64]; int i; ctlr = edev->ctlr; for(i = 0; i < edev->nopt; i++){ if(strncmp(edev->opt[i], "essid=", 6) == 0){ snprint(buf, sizeof(buf), "essid %s", edev->opt[i]+6); if(!waserror()){ wifictl(ctlr->wifi, buf, strlen(buf)); poperror(); } } } } static void iwlpromiscuous(void *arg, int on) { Ether *edev; Ctlr *ctlr; edev = arg; ctlr = edev->ctlr; qlock(ctlr); ctlr->prom = on; rxon(edev, ctlr->wifi->bss); qunlock(ctlr); } static void iwlproc(void *arg) { Ether *edev; Ctlr *ctlr; Wifi *wifi; Wnode *bss; edev = arg; ctlr = edev->ctlr; wifi = ctlr->wifi; for(;;){ /* hop channels for catching beacons */ setled(ctlr, 2, 5, 5); while(wifi->bss == nil){ qlock(ctlr); if(wifi->bss != nil){ qunlock(ctlr); break; } ctlr->channel = 1 + ctlr->channel % 11; ctlr->aid = 0; rxon(edev, nil); qunlock(ctlr); tsleep(&up->sleep, return0, 0, 1000); } /* wait for association */ setled(ctlr, 2, 10, 10); while((bss = wifi->bss) != nil){ if(bss->aid != 0) break; tsleep(&up->sleep, return0, 0, 1000); } if(bss == nil) continue; /* wait for disassociation */ edev->link = 1; setled(ctlr, 2, 0, 1); while((bss = wifi->bss) != nil){ if(bss->aid == 0) break; tsleep(&up->sleep, return0, 0, 1000); } edev->link = 0; } } static void iwlattach(Ether *edev) { char name[32]; FWImage *fw; Ctlr *ctlr; char *err; RXQ *rx; TXQ *tx; int i, q; ctlr = edev->ctlr; qlock(ctlr); if(waserror()){ qunlock(ctlr); nexterror(); } if(ctlr->attached == 0){ if((csr32r(ctlr, Gpc) & RfKill) == 0){ print("#l%d: wifi disabled by switch\n", edev->ctlrno); error("wifi disabled by switch"); } if(ctlr->wifi == nil) ctlr->wifi = wifiattach(edev, transmit); if(ctlr->fw == nil){ fw = readfirmware(fwname[ctlr->type]); print("#l%d: firmware: %s, rev %ux, build %ud, size %ux+%ux+%ux+%ux+%ux\n", edev->ctlrno, fwname[ctlr->type], fw->rev, fw->build, fw->main.text.size, fw->main.data.size, fw->init.text.size, fw->init.data.size, fw->boot.text.size); ctlr->fw = fw; } rx = &ctlr->rx; rx->i = 0; if(rx->b == nil) rx->b = malloc(sizeof(Block*) * Nrx); if(rx->p == nil) rx->p = mallocalign(sizeof(u32int) * Nrx, 256, 0, 0); if(rx->s == nil) rx->s = mallocalign(Rstatsize, 16, 0, 0); if(rx->b == nil || rx->p == nil || rx->s == nil) error("no memory for rx ring"); memset(rx->s, 0, Rstatsize); for(i=0; ip[i] = 0; if(rx->b[i] != nil){ freeb(rx->b[i]); rx->b[i] = nil; } if(rbplant(ctlr, i) < 0) error("no memory for rx descriptors"); } for(q=0; qtx); q++){ tx = &ctlr->tx[q]; tx->i = 0; tx->n = 0; if(tx->b == nil) tx->b = malloc(sizeof(Block*) * Ntx); if(tx->d == nil) tx->d = mallocalign(Tdscsize * Ntx, 256, 0, 0); if(tx->c == nil) tx->c = mallocalign(Tcmdsize * Ntx, 4, 0, 0); if(tx->b == nil || tx->d == nil || tx->c == nil) error("no memory for tx ring"); memset(tx->d, 0, Tdscsize * Ntx); } if(ctlr->sched.s == nil) ctlr->sched.s = mallocalign(512 * nelem(ctlr->tx) * 2, 1024, 0, 0); if(ctlr->kwpage == nil) ctlr->kwpage = mallocalign(4096, 4096, 0, 0); if((err = niclock(ctlr)) != nil) error(err); prphwrite(ctlr, ApmgPs, (prphread(ctlr, ApmgPs) & ~PwrSrcMask) | PwrSrcVMain); nicunlock(ctlr); csr32w(ctlr, Cfg, csr32r(ctlr, Cfg) | RadioSi | MacSi); if((err = niclock(ctlr)) != nil) error(err); prphwrite(ctlr, ApmgPs, prphread(ctlr, ApmgPs) | EarlyPwroffDis); nicunlock(ctlr); if((err = niclock(ctlr)) != nil) error(err); csr32w(ctlr, FhRxConfig, 0); csr32w(ctlr, FhRxWptr, 0); csr32w(ctlr, FhRxBase, PCIWADDR(ctlr->rx.p) >> 8); csr32w(ctlr, FhStatusWptr, PCIWADDR(ctlr->rx.s) >> 4); csr32w(ctlr, FhRxConfig, FhRxConfigEna | FhRxConfigIgnRxfEmpty | FhRxConfigIrqDstHost | FhRxConfigSingleFrame | (Nrxlog << FhRxConfigNrbdShift)); csr32w(ctlr, FhRxWptr, (Nrx-1) & ~7); nicunlock(ctlr); if((err = niclock(ctlr)) != nil) error(err); if(ctlr->type != Type4965) prphwrite(ctlr, SchedTxFact5000, 0); else prphwrite(ctlr, SchedTxFact4965, 0); csr32w(ctlr, FhKwAddr, PCIWADDR(ctlr->kwpage) >> 4); for(q = (ctlr->type != Type4965) ? 19 : 15; q >= 0; q--) csr32w(ctlr, FhCbbcQueue + q*4, PCIWADDR(ctlr->tx[q].d) >> 8); nicunlock(ctlr); for(i = (ctlr->type != Type4965) ? 7 : 6; i >= 0; i--) csr32w(ctlr, FhTxConfig + i*32, FhTxConfigDmaEna | FhTxConfigDmaCreditEna); csr32w(ctlr, UcodeGp1Clr, UcodeGp1RfKill); csr32w(ctlr, UcodeGp1Clr, UcodeGp1CmdBlocked); ctlr->ie = Idefmask; csr32w(ctlr, Imr, ctlr->ie); csr32w(ctlr, Isr, ~0); if(ctlr->type >= Type6000) csr32w(ctlr, ShadowRegCtrl, csr32r(ctlr, ShadowRegCtrl) | 0x800fffff); bootfirmware(ctlr); postboot(ctlr); ctlr->bcastnodeid = -1; ctlr->bssnodeid = -1; ctlr->channel = 1; ctlr->aid = 0; setoptions(edev); snprint(name, sizeof(name), "#l%diwl", edev->ctlrno); kproc(name, iwlproc, edev); ctlr->attached = 1; } qunlock(ctlr); poperror(); } static void receive(Ctlr *ctlr) { Block *b, *bb; uchar *d, *dd, *cc; RXQ *rx; TXQ *tx; uint hw; rx = &ctlr->rx; if(rx->s == nil || rx->b == nil) return; for(hw = get16(rx->s) % Nrx; rx->i != hw; rx->i = (rx->i + 1) % Nrx){ uchar type, flags, idx, qid; u32int len; b = rx->b[rx->i]; if(b == nil) continue; d = b->rp; len = get32(d); d += 4; type = *d++; flags = *d++; USED(flags); idx = *d++; qid = *d++; if((qid & 0x80) == 0 && qid < nelem(ctlr->tx)){ tx = &ctlr->tx[qid]; if(tx->n > 0){ bb = tx->b[idx]; if(bb != nil){ tx->b[idx] = nil; freeb(bb); } /* paranoia: clear tx descriptors */ dd = tx->d + idx*Tdscsize; cc = tx->c + idx*Tcmdsize; memset(dd, 0, Tdscsize); memset(cc, 0, Tcmdsize); tx->n--; wakeup(tx); } } len &= 0x3fff; if(len < 4 || type == 0) continue; len -= 4; switch(type){ case 1: /* microcontroller ready */ setfwinfo(ctlr, d, len); break; case 24: /* add node done */ break; case 28: /* tx done */ break; case 102: /* calibration result (Type5000 only) */ break; case 103: /* calibration done (Type5000 only) */ break; case 130: /* start scan */ break; case 132: /* stop scan */ break; case 156: /* rx statistics */ break; case 157: /* beacon statistics */ break; case 161: /* state changed */ break; case 162: /* beacon missed */ break; case 192: /* rx phy */ break; case 195: /* rx done */ if(d + 2 > b->lim) break; d += d[1]; d += 56; case 193: /* mpdu rx done */ if(d + 4 > b->lim) break; len = get16(d); d += 4; if(d + len + 4 > b->lim) break; if((get32(d + len) & 3) != 3) break; if(ctlr->wifi == nil) break; if(rbplant(ctlr, rx->i) < 0) break; b->rp = d; b->wp = d + len; wifiiq(ctlr->wifi, b); continue; case 197: /* rx compressed ba */ break; } /* paranoia: clear the descriptor */ memset(b->rp, 0, Rdscsize); } csr32w(ctlr, FhRxWptr, ((hw+Nrx-1) % Nrx) & ~7); } static void iwlinterrupt(Ureg*, void *arg) { u32int isr, fhisr; Ether *edev; Ctlr *ctlr; edev = arg; ctlr = edev->ctlr; ilock(ctlr); csr32w(ctlr, Imr, 0); isr = csr32r(ctlr, Isr); fhisr = csr32r(ctlr, FhIsr); if(isr == 0xffffffff || (isr & 0xfffffff0) == 0xa5a5a5a0){ iunlock(ctlr); return; } if(isr == 0 && fhisr == 0) goto done; csr32w(ctlr, Isr, isr); csr32w(ctlr, FhIsr, fhisr); if((isr & (Iswrx | Ifhrx | Irxperiodic)) || (fhisr & Ifhrx)) receive(ctlr); if(isr & Ierr){ iprint("#l%d: fatal firmware error\n", edev->ctlrno); dumpctlr(ctlr); } ctlr->wait.m |= isr; if(ctlr->wait.m & ctlr->wait.w){ ctlr->wait.r = ctlr->wait.m & ctlr->wait.w; ctlr->wait.m &= ~ctlr->wait.r; wakeup(&ctlr->wait); } done: csr32w(ctlr, Imr, ctlr->ie); iunlock(ctlr); } static Ctlr* iwlpci(void) { void *mem; Pcidev *pdev; Ctlr *ctlr, **p; static int once; static Ctlr *iwlhead; if(once) return iwlhead; once = 1; p = &iwlhead; for(pdev = nil; pdev = pcimatch(pdev, 0, 0); ) { if(pdev->ccrb != 2 || pdev->ccru != 0x80) continue; if(pdev->vid != 0x8086) continue; switch(pdev->did){ default: continue; case 0x4229: /* WiFi Link 4965 */ case 0x4230: /* WiFi Link 4965 */ case 0x4236: /* WiFi Link 5300 AGN */ case 0x4237: /* Wifi Link 5100 AGN */ break; } /* Clear device-specific "PCI retry timeout" register (41h). */ if(pcicfgr8(pdev, 0x41) != 0) pcicfgw8(pdev, 0x41, 0); /* Clear interrupt disable bit. Hardware bug workaround. */ if(pdev->pcr & 0x400){ pdev->pcr &= ~0x400; pcicfgw16(pdev, PciPCR, pdev->pcr); } pcisetbme(pdev); pcisetpms(pdev, 0); ctlr = malloc(sizeof(Ctlr)); if(ctlr == nil) { print("etheriwl: unable to alloc Ctlr\n"); continue; } ctlr->port = pdev->mem[0].bar & ~0x0F; mem = vmap(pdev->mem[0].bar & ~0x0F, pdev->mem[0].size); if(mem == nil) { print("etheriwl: %T: can't map bars\n", pdev->tbdf); free(ctlr); continue; } ctlr->nic = mem; ctlr->pdev = pdev; ctlr->type = (csr32r(ctlr, Rev) >> 4) & 0xF; if(fwname[ctlr->type] == nil){ print("etheriwl: unsupported controller type %d\n", ctlr->type); vunmap(mem, pdev->mem[0].size); free(ctlr); continue; } *p = ctlr; p = &ctlr->link; } return iwlhead; } static int iwlpnp(Ether* edev) { Ctlr *ctlr; ctlr = iwlpci(); again: for(; ctlr != nil; ctlr = ctlr->link){ if(ctlr->active) continue; if(ethercfgmatch(edev, ctlr->pdev, ctlr->port) == 0){ ctlr->active = 1; break; } } if(ctlr == nil) return -1; edev->ctlr = ctlr; edev->port = ctlr->port; edev->irq = ctlr->pdev->intl; edev->tbdf = ctlr->pdev->tbdf; edev->arg = edev; edev->interrupt = iwlinterrupt; edev->attach = iwlattach; edev->ifstat = iwlifstat; edev->ctl = iwlctl; edev->promiscuous = iwlpromiscuous; edev->multicast = nil; edev->mbps = 10; if(iwlinit(edev) < 0){ edev->ctlr = nil; ctlr = ctlr->link; goto again; } return 0; } void etheriwllink(void) { addethercard("iwl", iwlpnp); }